1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) panel such as a thin film transistor, low voltage differential signaling, display interface (TFT-LDI), and more particularly, to a display circuit capable of minimizing an arrangement area required to drive a display panel and a method of driving the display panel using the display circuit.
2. Description of the Related Art
In a gate driver and a source driver used to drive an LCD panel, the gate driver sequentially activates gate lines of the panel, and the source driver transfers data to cells connected to the activated gate lines.
FIG. 1 is a circuit diagram of a conventional source driver 100. Referring to FIG. 1, color data that indicates color to be displayed on a panel 102 includes three channel data, red (R) channel data DATA_R, green (G) channel data DATA_G, and blue (B) channel data DATA_B. When the three channel data are supplied to a cell of the panel 102, the cell produces a color.
A decoder DR receives the R channel data DATA_R and generates a corresponding R voltage signal R_VOL. The R voltage signal R_VOL is output after being buffered by an R buffer R_BUF. An output node RBON of the R buffer R_BUF and an R output node ROUT are connected or disconnected by a switch R_SW controlled by a connection control signal R_COCON.
If the switch R_SW is closed, the R voltage signal R_VOL is supplied to a corresponding cell R of the panel 102.
A decoder DG receives the G channel data DATA_G and generates a corresponding G voltage signal G_VOL. The G voltage signal G_VOL is output after being buffered by a G buffer G_BUF. An output node GBON of the G buffer G_BUF and a G output node GOUT is connected or disconnected by a switch G_SW controlled by a connection control signal G_COCON.
If the switch G_SW is closed, the G voltage signal G_VOL is supplied to a corresponding cell G of the panel 102.
A decoder DB receives the B channel data DATA_B and generates a corresponding B voltage signal B_VOL. The B voltage signal B_VOL is output after being buffered by a B buffer B_BUF. An output node BBON of the B buffer B_BUF and a B output node BOUT is connected or disconnected by a switch B_SW controlled by a connection control signal B_COCON.
If the switch B_SW is closed, the B voltage signal B_VOL is supplied to a corresponding cell B of the panel 102.
The R voltage signal R_VOL, the G voltage signal G_VOL, and the B voltage signal B_VOL are supplied to the same cell to make the cell produce a color. The source driver 100 includes a plurality of the decoders DR, DG, and DB, the buffers R_BUF, G_BUF, and B_BUF, and the switches R_SW, G_SW, and B_SW corresponding to the channel data DATA_R, DATA_G, and DATA_B in a number equal to the number of source lines of the panel 102.
The decoder DR, the R buffer R_BUF, and the switch R_SW that receive the R channel data DATA_R and supply the received data to a corresponding cell form a channel. Therefore, three channels are required for a cell to produce a color.
When image data is displayed on a display panel, the displayed color in a cell is usually similar to the color produced by neighboring cells. To be more specific, video and picture data along with image data are usually similar in a group of neighboring cells in a predetermined region. Thus, current is wasted when buffers of the R, G, and B channels of all of the source lines are driven.
To reduce this waste of current, when data or colors of two neighboring cells are identical, buffers of the neighboring cells are driven to output the same data.
FIG. 2 is a circuit diagram of a conventional display panel driving circuit using a reduced amount of current. The conventional display panel driving circuit 200 drives a buffer corresponding to a cell according to whether neighboring cells are to produce the same color. Referring to FIG. 2, the display panel driving circuit 200 includes an internal memory 202, a source driver 204, and a panel 206. The source driver 204 includes a latch unit 208, a data comparator 210, channel buffers R0_BUF through B1_BUF, and a plurality of switches R_A, G_A, B_A, R_B, G_B, B_B, R_C, G_C, and B_C.
The switch R_A is connected between a first R channel buffer R0_BUF and an R channel line of a first source line, the switch G_A is connected between a first G channel buffer G0_BUF and a G channel line of the first source line; the switch B_A is connected between a first B channel buffer B0_BUF and a B channel line of the first source line, the switch R_B is connected between a second R channel buffer R1_BUF and an R channel line of a second source line, the switch G_B is connected between a second G channel buffer G1_BUF and a G channel line of the second source line, the switch B_B is connected between a second B channel buffer B1_BUF and a B channel line of the second source line, the switch R_C is connected between an output node of the switch R_A and an output node of the switch R_B, the switch G_C is connected between an output node of the switch G_A and an output node of the switch G_B, and the switch B_C is connected between an output node of the switch B_A and an output node of the switch B_B.
The source driver 204 is a unit source driver including two source lines R0, G0, B0 and R1, G1, B1 in parallel connected therebetween. The unit source driver constitutes a pre-source driver of the display panel driving circuit 200. It is assumed that channel data of each cell includes 6 bits of data.
The operation of the conventional display panel driving circuit 200 will now be described with reference to FIG. 2. The internal memory 202 sequentially stores image data input externally in cell units. The internal memory 202 sequentially stores in order R0 channel data, G0 channel data, B0 channel data, R1 channel data, G1 channel data, and B1 channel data for a cell. The latch unit 208 latches 18-bit data read from the internal memory 202 and simultaneously outputs a first switching signal A. The data comparator 210 compares each of the channel data output from the latch unit 208 and determines whether two source lines have the same image data. For such a determination, the data comparator 210 determines whether the respective channel data of each source line are identical. To be more specific, the data comparator 210 compares 6-bit first R channel data R0<6> with 6-bit second R channel data R1<6>, compares 6-bit first G channel data G0<6> with 6-bit second G channel data G1<6>, and compares 6-bit first B channel data B0<6> with 6-bit second B channel data B1<6>.
The data comparator 210 determines that data transferred to two neighboring cells are identical if the channel data matches from an MSB (most significant bit) to an LSB (least significant bit). The data comparator 210 outputs a second switching signal B if the data are determined to be different, and outputs a third switching signal C if the data are determined to be identical.
If the data are determined to be identical, the channel buffers R0_BUF, G0_BUF, and B0_BUF corresponding to the first source line are activated and the channel buffers R1_BUF, G1_BUF, and B1_BUF corresponding to the second source line are deactivated.
The switches R_A, G_A, and B_A are closed in response to the first switching signal A, the switches R_B, G_B, and B_B are closed in response to the second switching signal B, and the switches R_C, G_C, and B_C are closed in response to a third switching signal C. Therefore, when the data are determined to be identical, the switches R_A, G_A, B_A, R_C, G_C, and B_C are closed, and the switches R_B, G_B, and B_B are opened. As a result, the channel data output in the channel buffers R0_BUF, G0_BUF, and B0_BUF corresponding to the first source line can be transmitted to the first and second source lines.
If image data of neighboring cells are identical, buffers corresponding to a cell are driven to display an image. The display panel driving circuit 200 can reduce current consumption by 25% for a white pattern or a black pattern.
However, since the display panel driving circuit 200 compares each bit of the MSB/LSB of each channel using the data comparator 210, lines connecting the latch unit 208 and the data comparator 210 are connected to input image data output from the latch unit 208 in the same channel, as shown in FIG. 2. To be more specific, the inputs of the 6-bit second R channel data R1<6>, the second G channel data G1<6>, and the second B channel data B1<6> are connected to the inputs of the 6-bit first R channel data R0<6>, the 6-bit first G channel data G0<6> and the 6-bit first B channel data B0<6>, respectively. Therefore, a routing space between the latch unit 208 and the data comparator 210 is expanded. For example, when a display panel driving circuit includes the data comparator 210 with a height of 35 μm, the routing space is 17.5 μm, which occupies more than half of the height.
It is also difficult to use only one buffer (or amplifier) in the conventional display panel driving circuit when handling N channels.